1) Field of the Invention
The present invention relates to a technology for calculating a wiring capacitance efficiently without loosing accuracy by reducing a size of a capacitance value table.
2) Description of the Related Art
When designing a large-scale-integration (LSI), a speed of a signal propagating through a transistor and a wiring is calculated to confirm that the LSI operates at an estimated speed. The wiring is represented by a model of resistance and capacitance, and a resistance value depends only on a shape of the wiring targeted for calculation of signal propagation time (hereinafter, “a target wiring”). However, a capacitance value depends on a state of arrangement of wirings above, below, on the left of, and on the right of the target wiring and in diagonally upward and downward directions from the target wiring (hereinafter, “an adjacent wiring”) including the target wiring.
Therefore, conventionally, capacitance values based on arrangement patterns of the adjacent wirings above, below, on the left of, and on the right of the target wiring and in the diagonally upward and downward directions from the target wiring are stored as a capacitance value table, and a wiring capacitance conforming to a wiring pattern in the capacitance value table is used as a capacitance value of the target wiring based on arrangement information of the adjacent wirings (see, for example, U.S. Pat. No. 6,185,722 and Habitz, Bill Livingstone, Laura Darden, Paul Zuchowski “IBM ASICs Redefine Performance Standard for Parasitic Extraction”, IBM Microelectronics, Vol. 7, No. 4).
However, since there are an enormous number of wiring patterns of adjacent wirings that affect a capacitance value of a target wiring, there is a problem in that it takes time to create a capacitance value table and a size of the capacitance value table to be created increases. It is anticipated that, in future, the size of the capacitance value table further increases when the number of wiring layers increases to create an LSI of higher performance.
Although, it is possible to reduce the number of wiring patterns and the size of the capacitance value table by neglecting patterns of adjacent wirings arranged in the diagonally upward and downward directions from the target wiring, this results in a degradation of accuracy in calculation of the wiring capacitance.